|Academic Profile |
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Assoc Prof Ang Diing Shenp
Associate Professor, School of Electrical & Electronic Engineering
|Dr. Ang obtained both his B. Eng. (hons) and Ph.D. degrees in electrical engineering from the National University of Singapore. He joined the School of EEE, NTU in July 2002 as an assistant professor and was promoted to associate professor in April 2008. Dr. Ang’s research interests lie mainly in device reliability physics and characterization. He has recently become interested in the applications of nano-characterization techniques and silicon nanostructures. Together with his graduate student, their work on the application of scanning probe techniques to study electronic trap generation in alternative high-k dielectrics won them the Bronze prize in the category of Physics, Chemistry of Material for Nano-Scale Devices of the 3rd TSMC Outstanding Student Research Award. Dr. Ang was invited to serve on the technical program committees of the International Reliability Physics Symposium from 2004-2006, and has served on the technical program committees nternational Symposium on the Physical and Failure Analysis of Integrated Circuits since 2004.|
|1. Reliability physics and characterization of nanoscale transistors (negative-bias temperature instability, hot-carrier effects, gate oxide breakdown, low frequency/RF noise, metal gate/high-kappa gate stack, non-volatile memories, silicon-on-insulator transistors, nanowire devices etc.)
2. Nano-characterization techniques (conductive atomic force microscopy, high-resolution transmission electron microscopy and associated anaytical techniques for alternative gate dielectrics, nanowire devices etc.)
3. Characterization of novel devices (e.g. tunneling FETs, novel memories etc.)
- Negative Photoconductance/optical Memory of Soft-breakdown Wide-bandgap Oxides
- To Enable A High-performance Power Amplifier Device on Thin-film SOI Through Device Engineering
- Towards a New Digital Image Sensor Based on the Negative Photoconductivity Effect in The Soft-Breakdown Oxide
- Understanding Charge-trapping Evolution In Small-dimension Logic/Memory Devices
- C. J. Gu, D. S. Ang, Y. Gao, R. Y. Gu, Z. Q. Zhao, and C. Zhu. (2017). A vacancy-interstitial defect pair model for positive-bias temperature stress induced electron trapping transformation in the high-k gate n-MOSFET. IEEE Transactions on Electron Devices, 64(6), TBD.
- Y. Zhou, T. Kawashima, and D. S. Ang. (2017). TiN-mediated multi-level negative photoconductance of the ZrO2 breakdown path. IEEE Journal of the Electron Devices Society, 5(3), 188-192.
- H. Z. Zhang, D. S. Ang, K. S. Yew, and X. P. Wang. (2016). Observation of self-reset during forming of the TiN/HfOx/TiN resistive switching device. IEEE Electron Device Letters, 37(9), 1116-1119.
- Z. Y. Tung and D. S. Ang. (2016). Impact of voltage-accelerated stress on hole trapping at operating condition. IEEE Electron Device Letters, 37(5), 644-647.
- A. A. Boo, Z. Y. Tung, and D. S. Ang. (2016). On the correlation between hole-trapping transformation and SILC generation under NBTI stressing. IEEE Electron Device Letters, 37(4), 369-372.
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