|Asst Prof Yu Yajun |
Division of Circuits & Systems
School of Electrical & Electronic Engineering
College of Engineering
Phone: (+65)6790 4389
- PhD National University of Singapore 2004
- ME Zhejiang University 1997
- BS Zhejiang University 1994
|Dr. Ya Jun Yu received both the B.Sc. and M.Eng. degrees in biomedical engineering from Zhejiang University, Hangzhou, China, in 1994 and 1997, respectively, and the Ph.D. degree in electrical and computer engineering from the National University of Singapore, Singapore, in 2004. |
Since 2005, she has been with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, where she is currently an Assistant Professor. From 1997 to 1998, she was a Teaching Assistant with Zhejiang University. She was a research engineer in the Department of Electrical and Computer Engineering, National University of Singapore from 1998 to 2004. In 2002, she was a Visiting Researcher at the Tampere University of Technology, Tampere, Finland and the Hong Kong Polytechnic University, Hong Kong, China. She joined the Temasek Laboratories at Nanyang Technological University as a Research Fellow in 2004. In 2009, she was a visiting professor at Curtin University of Technology, Perth, Australia. Her research interests include digital signal processing and VLSI circuits and systems design.
Dr. Yu has served as an associate editor for Circuits, Systems and Signal Processing, and IEEE Trans. on Circuits and Systems II, since 2009 and 2010, respectively. Dr. Yu is a senior member of IEEE.
|VLSI digital signal processing and circuits and systems|
|Research Grant |
- Academic Research Fund Tier 1 (2014-2016) [by Nanyang Technological University]
- Defence Research and Technology Office (DRTech) (2011-)
- Temasek Lab@NTU Seed Project (2006-2015) [by Temasek Lab @ NTU]
|Current Projects |
- Circuit and System Design for Digital Signal Processing.
- Design of very Low Complexity Digital Filters using Subexpression Sharing Techniques.
- Investigation, Design and Optimization of Non-uniformly Sampled Signal Processing System
- Sub Project 1-Sampling Rate Converter (SRC) & its FPGA implementation
- Y. J. Yu, and W. J. Xu. (2012). Mixed-Radix Fast Filter Bank Approach for the Design of Variable Digital Filters with Simultaneously Tunable Bandedge and Fractional Delay. IEEE Transactions on Signal Processing, 60(1), 100-111.
- D. Shi and Y. J. Yu. (2011). Design of Discrete-valued Linear Phase FIR Filters in Cascade Form. IEEE Transactions on Circuits and Systems I-Regular Papers, 58(7), 1627-1636.
- R. Bregovic, Y. J. Yu, T. Saramäki and Y. C. Lim. (2011). Implementation of Linear-Phase FIR Filters for a Rational Sampling Rate Conversion Utilizing the Coefficient Symmetry. IEEE Transactions on Circuits and Systems I-Regular Papers, 58(3), 548-561.
- D. Shi and Y. J. Yu. (2011). Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders. IEEE Transactions on Circuits and Systems I-Regular Papers, 58(1), 126-136.
- Y. J. Yu, D. Shi, and Y.C. Lim. (2009). Design of Extrapolated Impulse Response FIR Filters with Residual Compensation in Subexpression Space. IEEE Transactions on Circuits and Systems I-Regular Papers, 56(12), 2621 - 2633.