|Asst Prof Kim Tae Hyoung |
Division of Circuits & Systems
School of Electrical & Electronic Engineering
College of Engineering
Phone: (+65)6790 4001
- PhD (ElectEng) University of Minnesota 2009
- MS (ElectEng) Korea University 2001
- BS (ElectEng) Korea University 1999
|Prof. Tony T. Kim received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, Korea, in 1999 and 2001, respectively. He received the Ph.D. degree in electrical and computer engineering from University of Minnesota, Minneapolis, MN, USA in 2009. From 2001 to 2005, he worked for Samsung Electronics where he performed research on the design of high-speed SRAM memories, clock generators, and IO interface circuits. In 2007 ~ 2009 summer, he was with IBM T. J. Watson Research Center and Broadcom Corporation where he performed research on isolated NBTI/PBTI measurement circuits and SRAM Mismatch measurement test structure, and battery backed memory design, respectively. In November 2009, he joined Nanyang Technological University as an assistant professor.
Prof. Kim received 2008 AMD/CICC Student Scholarship Award, 2008 Departmental Research Fellowship from U. of Minnesota, 2008 DAC/ISSCC Student Design Contest Award, 2008 Samsung Humantec Thesis Award (Bronze Prize), 2005 ETRI Journal Paper of the Year Award, 2001 Samsung Humantec Thesis Award (Honor Prize), and 1999 Samsung Humantec Thesis Award (Silver Prize). His current research interests include low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage sub-threshold circuit design for energy efficiency, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs. He is a member of IEEE.
|Low power and high performance digital, mixed-mode, and memory circuit design, ultra-low voltage sub-threshold circuit design for energy efficient systems, variation and aging tolerant circuits and systems, and circuit techniques for 3D ICs.|
|Research Grant |
- A*STAR Science and Engineering Research Council (2011-2014) [by A*STAR Science & Engineering Research Council (SERC)]
- Academic Research Fund Tier 1 (2011-2014) [by Nanyang Technological University]
- Academic Research Fund Tier 1 (2012-2015) [by Nanyang Technological University]
- Start Up Grant (2009-2013) [by Nanyang Technological University, School of Electrical and Electronic Engineering]
|Current Projects |
- Design of Highly Energy Efficient Ultra-low Voltage Memories for Battery- or Self-powered Micro-watt Applications
- Design of Low Voltage, Low Power Circuits and Systems with Variation Tolerance
- NEMS Memory Array Design
- Stochastic CMOS Computing: Thriving on Variability in Nano-Scale CMOS and Beyond
- Anh Tuan Do, Karthik G. Jayaraman, Vincent Pott, Geng L. Chua, Pushpapraj Singh, Kiat S. Yeo and Tony T. Kim,. (2013). An Improved Read/Write Scheme for Anchorless NEMS-CMOS Non-Volatile Memory. 2013 IEEE International Symposium on Circuits and Systems, Beijing, China,.
- Anh Tuan Do, Truc Quynh Nguyen, Kiat Seng Yeo, and Tony Tae Hyoung Kim,. (2012). Sensing Margin Enhancement Techniques for Ultra-low Voltage SRAMs Utilizing Bitline Boosting Current and Equalized Bitline Leakage. IEEE Transactions on Circuits and Systems Part II-Express Briefs, 59(12), 868-872.
- Z. Lee, K. Ho, Z. Kong, and T. Kim,. (2012). NBTI/PBTI-Aware Wordline Voltage Control with No Boosted Supply for Stability Improvement of Half-Selected SRAM Cells. International SoC Design Conference (ISOCC), (pp. 200-203).
- B. Wang, T. Nguyen, A. Do, J. Zhou, M. Je, and T. Kim. (2012). A 0.2V 16Kb 9T SRAM with Bitline Leakage Equalization and CAM-assisted Write Performance Boosting for Improving Energy Efficiency. IEEE Asian Solid-State Circuits Conference (A-SSCC) (pp. 73-76).
- T. Kim, B. Wang, and A. T. Do. (2012). High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture. International SoC Design Conference (ISOCC), Nov. 2012 (pp. 367-370).