|Assoc Prof Ang Diing Shenp |
Assistant Head, Division of Microelectronics
Deputy Director, NOVITAS, Nanoelectronics Centre of Excellence
Division of Microelectronics
School of Electrical & Electronic Engineering
College of Engineering
Phone: (+65)6790 6023
- PhD National University of Singapore 1998
- BEng(Hons) National University of Singapore 1994
|Dr. Ang obtained both his B. Eng. (hons) and Ph.D. degrees in electrical engineering from the National University of Singapore. He joined the School of EEE, NTU in July 2002 as an assistant professor and was promoted to associate professor in April 2008. Dr. Ang’s research interests lie mainly in device reliability physics and characterization. He has recently become interested in the applications of nano-characterization techniques and silicon nanostructures. Together with his graduate student, their work on the application of scanning probe techniques to study electronic trap generation in alternative high-k dielectrics won them the Bronze prize in the category of Physics, Chemistry of Material for Nano-Scale Devices of the 3rd TSMC Outstanding Student Research Award. Dr. Ang was invited to serve on the technical program committees of the International Reliability Physics Symposium from 2004-2006, and has served on the technical program committees nternational Symposium on the Physical and Failure Analysis of Integrated Circuits since 2004.|
|1. Reliability physics and characterization of nanoscale transistors (negative-bias temperature instability, hot-carrier effects, gate oxide breakdown, low frequency/RF noise, metal gate/high-kappa gate stack, non-volatile memories, silicon-on-insulator transistors, nanowire devices etc.)
2. Nano-characterization techniques (conductive atomic force microscopy, high-resolution transmission electron microscopy and associated anaytical techniques for alternative gate dielectrics, nanowire devices etc.)
3. Characterization of novel devices (e.g. tunneling FETs, novel memories etc.)
|Research Grant |
- Academic Research Fund Tier 1 (2013-2014) [by Ministry of Education (MOE)]
- Academic Research Fund Tier 2 (2009-2013) [by MOE]
- Micron Technology Foundation Inc (2012-2014) [by Micron Technology Foundation Inc]
|Current Projects |
- Exploring the Physics of the Metal-Oxide Resistive Memory through Atomic Scale Characterization
- High-performance Future-generation Metal-insulator-metal Capacitors and Metal-oxide-semiconductor Gate Stacks Based On Multilayer Ternary/quaternary Metal-oxide Dielectrics
- Physics and Atomistic Modeling of Dielectric/ Semiconductor Interface Instability
- Y. Gao, D. S. Ang and C. J. Gu. (2013). ECS Transactions: On the Evolution of Switching Oxide Traps in the HfO2/TiN Gate Stack Subjected to Positive- and Negative-Bias Temperature Stressing. 223rd ECS Meeting (pp. 205-220).
- Y. Gao, D. S. Ang, G. Bersuker, and C. D. Young. (2013). Electron Trap Transformation under Positive-Bias Temperature Stressing. IEEE Electron Device Letters, 34(3), 351-353.
- Z. Q. Teo, D. S. Ang, and C. M. Ng. (2010). Separation of hole trapping and interface state generation by ultrafast measurement on dynamic negative-bias temperature instability. IEEE Electron Device Letters, , Accepted.
- D. S. Ang, Z. Q. Teo, T. J. J. Ho, and C. M. Ng. (2010). Reassessing the mechanisms of negative-bias temperature instability by repetitive stress/relaxation experiments. IEEE Transactions on Device and Materials Reliability, , Accepted.
- Y. Z. Hu, D. S. Ang, Z. Q. Teo, and G. A. Du. (2010). A robust ultrafast switching methodology for device parameter charactrization of bias-temperature instability. 48th International Reliability Physics Symposium.