|Academic Profile |
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Asst Prof Kim Bongjin
Assistant Professor, School of Electrical & Electronic Engineering
Phone: +65 67906461
Office: S2 B2B 60
|Prof. Bongjin Kim received BS and MS degrees from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2004 and 2006, respectively and PhD degree from University of Minnesota, Minneapolis, MN, USA in 2014. After PhD, He spent two years at Rambus Inc., CA where he was a senior technical staff member and worked on research of high-speed serial link circuits and micro-architectures. After working as a postdoctoral research fellow at Stanford University for a year, he joined Nanyang Technological University as an Assistant Professor in Sep. 2017.|
From 2006 to 2010, he was with System LSI, Samsung Electronics, Yongin, South Korea, where he performed research on clock generator circuits for high-speed serial links. In 2012, he joined Wireless Business, Texas Instruments, Dallas, TX, USA as a SRC Summer Intern. He also joined Mixed-Signal Communication IC Design Group, IBM T.J. Watson Research Center as a Research Summer Intern in 2013. He was an Engineering Intern in Memory and Interface Division, Rambus Inc., Sunnyvale, CA, USA in 2014, where he was involved in the research of 28/56Gbps serial link circuits and microarchitectures.
Prof. Kim is the receipent of a Doctoral Dissertation Fellowship Award, a ISLPED Low Power Design Contest Award and a Intel/IBM/Catalyst Foundation CICC Student Award. His research works appeared in top circuit conferences and journals including ISSCC, VLSI symposium, CICC and JSSC.
|VLSI Circuit Research (Analog, Mixed-Signal and Digital Circuits)|
1) Design techniques and methodologies for wireline communication circuits and systems
2) Data converters and clock synthesizers for wireline, wireless and computing applications
3) Machine learning hardware implementation using analog/mixed-signal and digital circuit techniques
4) Low-power integrated circuits for biomedical and IoT applications
- Design Techniques and Methodologies for Digital-intensive Wireline Communication Circuits and Systems
- Time-based Integrated Circuit Designs For Low Voltage On-chip Communication Systems
- S. Kundu, B. Kim, C. H. Kim. (2016). A 0.2-1.45GHz Sub-sampling Fractional-N All-Digital MDLL with Zero-offset Aperture PD based Spur Cancellation and In-situ Timing Mismatch Detection, IEEE International Solid-State Circuits Conference (ISSCC).
- B. Kim, H. Kim, C. H. Kim. (2015). An 8bit, 2.6ps Two-Step TDC in 65nm CMOS Employing a Switched Ring-Oscillator Based Time Amplifier, IEEE Custom Integrated Circuits Conference (CICC).
- B. Kim, S. Kundu, C. H. Kim. (2015). A 0.4-1.6GHz Spur-Free Bang-Bang Digital PLL in 65nm with a D-Flip-Flop Based Frequency Subtractor Circuit, Symposium on VLSI Circuits (SOVC).
- B. Kim, W. Xu, C. H. Kim. (2014). A Supply-Noise Sensitivity Tracking PLL in 32nm SOI Featuring a Deep Trench Capacitor Based Loop Filter. IEEE Journal of Solid-State Circuits, VOL. 49, 1017-1026.
- B. Kim, W. Xu, C. H. Kim. (2013). A 32nm, 0.9V Supply-Noise Sensitivity Tracking PLL for Improved Clock Data Compensation Featuring a Deep Trench Capacitor Based Loop Filter, Symposium on VLSI Circuits (SOVC).