|Academic Profile |
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Assoc Prof Lau Kim Teen
Associate Professor, Centre for Professional and Continuing Education
Phone: +65 67905420
Office: S1 B1A 12
|KT Lau previously served as program director of two Master of Science programs at the School of Electrical and Electronic Engineering. He has worked in multinational corporations in Santa Clara, California (Silicon Valley) and Bayan Lepas, Penang, where he was involved in the design of digital CMOS microchips and the production of microelectronics/optoelectronics products. He was at ESIEE Paris on an academic exchange program. KT has published more than 100 papers in international journals and conference proceedings, and is a reviewer for more than 20 international publications, including various IEEE, IEE/IET publications and other international journals and conferences, has served as an external assessor for a research funding agency and external examiner for graduate-level theses and dissertations. He currently teaches undergraduate and graduate-level courses in electronics and integrated circuit design at the School of Electrical and Electronic Engineering. KT was awarded the Pingat Bakti Setia (MoE) and received academic degrees from Cornell University.|
|Ultra Low Power IC Design|
Adiabatic CMOS Circuit Design
Self-Timed CMOS Circuit Design
Radiation-hardened CMOS Circuit Design
CMOS Circuits for IoT Applications
- Irina Alam and KT Lau. (2017). Approximate Adder for Low Power Computations. International Journal of Electronics Letters, 5(2), 158-165.
- Yang Shaochen, Lau KT and Zhang Yufei. (2016). Design of Low Power CMOS Parallel Prefix Adder Cell. Journal of Electrical Engineering and Electronic Technology, 5(1).
- Ramakrishnan S and Lau K T. (2008). Improved Dynamic Current Mode Logic for Low Power Applications. Journal of Circuits Systems and Computers, 17(2), 183-190.
- Ng K W and Lau K T. (2000). A Novel Adiabatic Register File Design. Journal of Circuits Systems and Computers, 10(1-2), 67-76.
- Liu F and Lau K T. (1998). Pass-Transistor Adiabatic Logic with NMOS Pull-down Configuration. Electronics Letters, 34(8), 739-741.
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