Academic Profile

Academic Profile

Assoc Prof Lau Kim Teen

Associate Professor

Phone: (+65)6790 5420
Office: S1-B1a-12

  • MEng Cornell University 1984
  • BSEE Cornell University 1983
KT Lau previously served as program director of two Master of Science programmes at the School of Electrical and Electronic Engineering. He has worked in MNCs [National Semiconductor (now Texas Instruments) and Hewlett-Packard], in Santa Clara, California and in Penang, Malaysia, where he was involved in microchip design and microelectronics/optoelectronics manufacturing. He was at ESIEE Paris on a faculty exchange programme. KT has published more than 100 papers in international journals and conference proceedings, and is a reviewer for various IEEE, IEE/IET publications and other international journals and conferences, has served as external assessor for Research Grants Council of Hong Kong and external examiner for graduate-level theses and dissertations. He currently teaches undergraduate and graduate-level courses in electronics and integrated circuit design at the School of Electrical and Electronic Engineering. KT attended Cornell on a university undergraduate scholarship and graduate fellowship.
Research Interests
Ultra Low Power IC Design
Adiabatic CMOS Circuit Design
Self-Timed CMOS Circuit Design
Radiation-hardened CMOS Circuit Design
CMOS Circuits for IoT Applications
Selected Publications
  • Irina Alam and KT Lau. (2017). Approximate Adder for Low Power Computations. International Journal of Electronics Letters, 5(2), 158-165.
  • Yang Shaochen, Lau KT and Zhang Yufei. (2016). Design of Low Power CMOS Parallel Prefix Adder Cell. Journal of Electrical Engineering and Electronic Technology, 5(1).
  • Ramakrishnan S and Lau K T. (2008). Improved Dynamic Current Mode Logic for Low Power Applications. Journal of Circuits Systems and Computers, 17(2), 183-190.
  • Ng K W and Lau K T. (2000). A Novel Adiabatic Register File Design. Journal of Circuits Systems and Computers, 10(1-2), 67-76.
  • Liu F and Lau K T. (1998). Pass-Transistor Adiabatic Logic with NMOS Pull-down Configuration. Electronics Letters, 34(8), 739-741.

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