|Academic Profile |
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Asst Prof Anupam Chattopadhyay
School of Computer Science and Engineering
College of Engineering
Phone: (+65)6790 6092
- Dr.-Ing. RWTH Aachen University 2008
- MSc. ALaRI, USI 2002
- BE Jadavpur University 2000
|Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India, MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2000, 2002 and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September, 2014, he is appointed as an assistant Professor in SCSE, NTU and also holds an honorary adjunct appointment at SPMS, NTU. In the past, he was visiting Professor at EPFL, Switzerland and Indian Statistical Institute, Kolkata.|
During his doctoral studies, he worked on automatic RTL generation from the architecture description language LISA, which led to a spin-off, and subsequently was acquired by a leading EDA vendor. He developed novel high-level optimisations, verification techniques, and proposed a language-based modelling, exploration and design framework for partially re-configurable processors - many of which resulted in successful technology transfers to the EDA and Semiconductor IP industry.
Anupam currently heads a team of 20+ researchers, overseeing projects in the area of computer architectures, security, design automation and emerging technologies. His research advances has been reported in more than 100 conference/journal papers (ACM/IEEE/Springer), multiple research monographs and edited books (CRC, Springer) and open-access forums. Together with his doctoral students, Anupam proposed novel research directions like, domain-specific high-level synthesis for cryptography, high-level reliability estimation flows for embedded processors, generalisation of classic linear algebra kernels and multi-layered coarse-grained reconfigurable architecture. Anupam’s research in the area of emerging technologies has been covered by major news outlets across the world, including Asian Scientist, Straits Times and The Economist.
Anupam regularly serves in the TPCs of top conferences, reviews journal/ conference articles and presented multiple invited seminars/tutorials in prestigious venues. He is a series editor of Springer book series on Computer Architecture and Design Methodologies. He is a member of ACM and a senior member of IEEE.
Anupam received Borcher's plaque from RWTH Aachen, Germany for outstanding doctoral dissertation in 2008, nomination for the best IP award in the ACM/IEEE DATE Conference 2016 and nomination for the best paper award in the International Conference on VLSI Design 2018.
- Bio-inspired agile cyber-security assurance framework (BICSAF)
- Cloud-enhanced Learning for Hardware-Oriented Labs in Computing
- Cybersecurity Protocol and Mechanism for e-Logistics of Dangerous Goods Tracking Using Block Chain
- Logic Synthesis Flow for Digital Design Technologies Beyond CMOS
- POSYN: Logic, Circuit and Architectural Synthesis for Post-CMOS Technologies; HAVIS: Development of customizable, accurate, efficient and scalable Hardware-Accelerated Virtual Screening Platform
- Productive Failure via Educational Games for Tertiary Education
- STRAIT: Secure and Privacy-Customizable Data Transmission for Internet-of-Things
- Sensing and Management for Agile Transportation (SMAT)
- Sparse-represented Non-volatile In-memory Accelerator for Big-Data Analytics
- To Research & Develop Assessment Tool and System – OpsTrace
- Prasanna Ravi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay. (2018). PPAP and iPPAP: PLL based Protection Against Physical attacks. IEEE Computer Society Annual Symposium on VLSI 2018.
- Pudi Vikramkumar, Anupam Chattopadhyay, Lam Kwok Yan. (2018). Efficient and Lightweight Quantized Compressive Sensing using u-Law. The International Symposium on Circuits and Systems (ISCAS) 2018.
- Anubhab Baksi, Vikramkumar Pudi, Swagata Mandal and Anupam Chattopadhyay. (2018). Lightweight ASIC Implementation of AEGIS-128. ISVLSI 2018.
- Mustafa Khairallah, Rajat Sadhukhan, Radhamanjari Samanta, Jakub Breier, Shivam Bhasin, Rajat Subhra Chakraborty, Anupam Chattopadhyay, Debdeep Mukhopadhyay. (2018). Design, Automation & Test in Europe Conference & Exhibition (DATE): DFARPA: Differential Fault Attack Resistant Physical Design Automation. Design, Automation & Test in Europe 2018 (DATE) (pp. 1--4)USA: IEEE.
- Haj-Yahya, Jawad and Mendelson, Avi and Asher, Yosi Ben and Chattopadhyay, Anupam. (2018). Energy Efficient High Performance Processors: Recent Approaches for Designing Green High Performance Computing. Springer.