|Anupam Chattopadhyay received his B.E. degree from Jadavpur University, India, MSc. from ALaRI, Switzerland and PhD from RWTH Aachen in 2000, 2002 and 2008 respectively. From 2008 to 2009, he worked as a Member of Consulting Staff in CoWare R&D, Noida, India. From 2010 to 2014, he led the MPSoC Architectures Research Group in RWTH Aachen, Germany as a Junior Professor. Since September, 2014, Anupam was appointed as an Assistant Professor in SCSE, NTU, where he got promoted to Associate Professor with Tenure from August, 2019. In the past, he held visiting positions at Politecnico di Torino, Italy; EPFL, Switzerland; Technion, Israel and Indian Statistical Institute, Kolkata.|
During his doctoral studies, he worked on automatic RTL generation from the architecture description language LISA, which led to a spin-off, and subsequently was acquired by a leading EDA vendor. He developed novel high-level optimisations, verification techniques, and proposed a language-based modelling, exploration and design framework for partially re-configurable processors - many of which resulted in successful technology transfers to the EDA and Semiconductor IP industry.
Anupam currently heads a team of 20+ researchers, overseeing projects in the area of computer architectures, security, design automation and emerging technologies. His research advances has been reported in more than 100 conference/journal papers (ACM/IEEE/Springer), multiple research monographs and edited books (CRC, Springer) and open-access forums. Together with his doctoral students, Anupam proposed novel research directions like, domain-specific high-level synthesis for cryptography, high-level reliability estimation flows for embedded processors, generalisation of classic linear algebra kernels and multi-layered coarse-grained reconfigurable architecture. Anupam’s research in the area of emerging technologies has been covered by major news outlets across the world, including Asian Scientist, Straits Times and The Economist.
Anupam regularly serves in the TPCs of top conferences, reviews journal/ conference articles and presented multiple invited seminars/tutorials in prestigious venues. He is a series editor of Springer book series on Computer Architecture and Design Methodologies. He is a member of ACM and a senior member of IEEE.
Anupam received Borcher's plaque from RWTH Aachen, Germany for outstanding doctoral dissertation in 2008, nomination for the best IP award in the ACM/IEEE DATE Conference 2016 and nomination for the best paper award in the International Conference on VLSI Design 2018.
- Prasanna Ravi, Debapriya Basu Roy, Shivam Bhasin, Anupam Chattopadhyay, Debdeep Mukhopadhyay. (2019). In International Workshop on Constructive Side-Channel Analysis and Secure Design: Number “Not Used” Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates. International Workshop on Constructive Side-Channel Analysis and Secure Design (pp. 232-250)Darmstadt, Germany: Springer.
- Jawad Haj-Yahya, Ming Ming Wong, Vikramkumar Pudi, Shivam Bhasin, Anupam Chattopadhyay. (2019). ISQED '19 Proceedings of the 20th international symposium on Quality Electronic Design: Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. 20th International Symposium on Quality Electronic Design (ISQED) (pp. 216-223)Santa Clara, USA: IEEE.
- N. Tian, V. T. Kanappan, Y. J. J. Hong, A. Fathima, O. N. N. Fernando, H. S. Soon, and A. Chattopadhyay. (2018). Proc. of the Asian Conference on Education (ACE2018): Manufactory: Promoting 3D Spatial Skills with Productive Failure and Educational Games. The Asian Conference on Education (ACE2018) (pp. 899 to 919)Nagoya, Aichi, Japan: The International Academic Forum.
- Srinivasu Bodapati, Vikramkumar pudi, Anupam chattopadhyay, Kwok Yan Lam. (2018). Asia Pacific Conference on Circuits and Systems (APCCAS): CoLPUF: A Novel Configurable LFSR-based PUF. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 358-361)China: IEEE.
- Prasanna Ravi, Shivam Bhasin, Jakub Breier, Anupam Chattopadhyay. (2018). PPAP and iPPAP: PLL based Protection Against Physical attacks. IEEE Computer Society Annual Symposium on VLSI 2018.